1. Technical Field
The present invention relates to integrated circuits, and more particularly to circuit self-repair to fully or partially recover damaged devices.
2. Description of the Related Art
As complementary metal oxide semiconductor (CMOS) technology generations advance into submicron and nanometer scale, CMOS-device threshold-voltage instability has become a major reliability problem. The threshold voltage (Vt) instability not only reduces the circuit's operation lifetime, but also adversely affects circuit yields. For example, in static random access memory (SRAM) fails occur during burn-in because of corresponding P-type field effect transistor (PFET) threshold degradation. In analog circuits, severe Vt mismatch could result in circuit failure.
It is known that one major cause of the threshold instability of PFETs is due to an effect called negative bias temperature instability (NBTI). NBTI has been widely investigated because it increases PFET threshold voltage and decreases the drive current due to the buildup of positive charge and surface states in the gate dielectric. As gate dielectric thickness is further reduced and new gate materials are employed, NBTI is becoming a more prominent degradation mechanism in PFET devices. Also, NBTI has become the major reliability issue at the circuit-level due to its large duty cycle under a relative bias between gate and drain in a specific waveform during circuit operation. NBTI is also independent of device channel length.
The analogous threshold instability of an N-type field effect transistor (NFET) is positive bias temperature instability (PBTI). Note that compared with NBTI and other device degradation mechanisms like hot electron wear-out effect, PBTI is less significant for traditional gate oxide devices. However, as high-dielectric constant (high-k) materials are introduced as the gate dielectric for advanced technologies, PBTI effects have a greater impact on the circuit and have to be taken into consideration during the course of process development.
Some degraded devices as a result of certain wear-out mechanisms can be recovered. For example, U.S. Pat. No. 4,238,694 discloses a method for recovering selected areas of a radiation damaged semiconductor by a high temperature bake. For NBTI, various methods have been practiced in the industry to minimize its detrimental effect on device performance during fabrication including tuning a thermal anneal time and hydrogen flow.
Device structures have also been used to reduce NBTI. For example, U.S. Pat. No. 7,030,498, titled “Semiconductor Device with Copper Wirings Having Improved Negative Bias Temperature Instability (NBTI)”, teaches the use of a diffusion barrier, such as silicon carbide (SiC), to suppress NBTI-induced threshold shifting. In U.S. Pat. No. 7,030,498, a PFET structure is disclosed, which includes a nitrogen-containing silicon oxide and a copper wiring pattern including an underlying barrier layer and a SiC layer covering the copper wiring pattern. This PFET structure attempts to suppress NBTI deterioration. This fix deviates from normal processing steps and requires new material which is not desirable from a cost point of view.
After device fabrication and stresses under NBTI conditions, thermal annealing was observed to partially recover the NBTI degradation. U.S. Pat. No. 6,958,621, entitled, “Method and Circuit for Element Wearout Recovery,” proposes a structure and methodology for circuit recovery after NBTI degradation. U.S. Pat. No. 6,958,621 utilizes an annealing effect for NBTI recovery by employing polysilicon heaters adjacent to the gates of critical devices. By powering up the heater, the channel temperature of the critical devices is raised to an annealing level so that the NBTI-induced interface damage can be partially removed. The drawbacks of this method include: (1) a large area is required for accommodating the heater components, (2) a slow thermal repairing process is needed, and (3) a large amount of power is consumed to reach the annealing condition.